1. Field
This disclosure relates generally to memories, and more specifically, to clocked memories with latching predecoder circuitry.
2. Related Art
Word selection is in the critical path for reading or writing a memory. The word line is selected which enables memory cells along the selected word line. The enabled memory cells couple their stored state to bit lines. Sense amplifiers then respond to the bit lines in the case of a read or write drivers provide data to be written onto the bit lines in the case of a write. Thus, as the process of word line selection is made more efficient, memory operation is correspondingly made more efficient. One of the difficulties is providing reliable timing, especially in initiating the process of selecting the word line. One problem that is relevant is the combination of when to respond to an address and when to provide a decoded output. Often this is controlled by a delayed clock signal which results in the issue of waiting logn enough to ensure that the signal is sufficiently developed to ensur that the signal detection is valid but not so long as to unnecessarily extend the time required to perform the detection.
Accordingly there is a need to provide word selection with circuitry that improves upon one or more of the issues raised above.